1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device provided with a data register for temporarily holding data in a burst accessing nonvolatile memory array.
2. Description of the Background Art
Conventionally, a static random access memory (hereinafter, referred to as SRAM) and the like has been operated in random access and a bit line pair has been precharged every reading or writing cycle.
Meanwhile, there is disclosed a method for reducing power consumption at precharging by reducing the number of precharge operations to the bit line pair performed every change in an address, in, for example, Japanese Patent Laying-Open No. 06-223576.
That is, according to Japanese Patent Laying-Open No. 06-223576, when an address A is changed at a period 2T for a RAM part having k×n pieces of RAM cells constituted of k pieces (e.g. four pieces) of bit line pairs and n pieces of word lines, the address A is accessed from 0, 1, 2, 3, . . . successively according to a characteristic of the address access to a line memory. Thus, the bit line pair on a row side is not accessed again until four times accesses after the bit line pair is accessed once. Therefore, an AND processing is performed by an original precharge signal φ1 and the address A so as to perform the precharge operation to the bit line pair only when a minimum address (e.g. 00) comes at accessing the row side, and a new precharge signal φ1a is formed to perform the precharge operations only at 0, 4, 8, . . . addresses according to the φ1a. 
Meanwhile, some electrically rewritable nonvolatile semiconductor memory devices such as a burst reading or writing flash memory are provided with a data register for temporarily holding read data from the flash memory and written data to the flash memory. When the data register includes a plurality of memory cells, the method disclosed in Japanese Patent Laying-Open No. 06-223576 is also used to reduce the power consumption by the bit line pair in the data register.
However, the method disclosed in Japanese Patent Laying-Open No. 06-223576 never perform precharging to the bit line pair until reaching a maximum column address and cannot cope with a case where it becomes necessary to precharge the bit line pair every reading or writing cycle.